As integrated circuit technology has advanced toward smaller device sizes, the industry has searched for ways of annealing ion implanted dopant impurities that minimize diffusion of the impurities. Such diffusion can distort (deepen) shallow junction implanted regions as a function of the time and temperature over which the implanted dopants are annealed. The annealing process repairs damage to the semiconductor crystal arising during ion implantation and activates the implanted semiconductor junctions by moving the implanted dopant atoms from interstitial sites to substitutional sites in the semiconductor crystal lattice. Conventional annealing methods have typically employed radiant lamps that heat the wafer to a sufficiently high temperature to achieve the desired effect. One such method holds the wafer at an elevated temperature for a relatively long (one to sixty second) period and produces a relatively large amount of implanted dopant diffusion. For smaller device sizes (e.g., 45 nm), a faster annealing process is desired, such as a spike anneal in which the wafer temperature is ramped up to an elevated temperature and then returned to its former temperature within half a second. An even faster process that can be suitable for device sizes at or below 45 nm is flash annealing, in which the wafer temperature is raised from 400° C. to 1100° C. and then returned to 400° C. within milliseconds. While flash annealing can achieve favorable results at 45 nm, it entails a higher risk of wafer breakage because of the sudden wafer temperature excursion. The need for a reliable post-implant annealing process that will work at the lowest device sizes that the industry is now contemplating (below 45 nm, e.g., 30 nm and 15 nm) has been recently met by the dynamic surface annealing (DSA) process. This process scans a powerful micron-thin line of monochromatic laser light across the wafer at a rate such that, at any instant, only a thin shallow region of the wafer is heated to near melting (e.g., 1300° C.) for an extremely short period of time (e.g., 100 μsec), this time being kept short because the entire remainder of the wafer serves as a heat sink for the heated zone. The result is little or no diffusion of the implanted dopant atoms, enabling realization of ultra-shallow implanted junction depths, and much less risk of wafer breakage. The DSA process is disclosed in U.S. Patent application publication No. US 2003/0196996, the entire disclosure of which is incorporated herein by reference.
Typically, the DSA process is carried out immediately after ion implantation of the dopant atoms in the semiconductor crystal. The DSA annealing step may be preceded by a short but lower temperature (e.g., 800° C.) annealing step using radiant lamps to repair ion implantation damage to the crystal. Typically, during the entire DSA step, an optical absorption layer such as amorphous carbon covers the wafer surface to provide uniform process results, the optical absorber layer being removed upon completion of the DSA step with a low temperature oxygen ashing.
Upon removal of the optical absorber layer, subsequent low temperature process steps that must be carried out require raising the wafer temperature above 400° C. for relatively long time frames, so that some of the implanted dopant atoms which were placed in substitutional crystalline sites return to interstitial sites, thereby deactivating a significant fraction of the dopants in the ion implanted regions (i.e., the source, drain and gate regions). These low temperature process steps include the formation of metal-silicide contacts on the top surfaces of the implanted regions, entailing deposition of a suitable metal followed by a rapid thermal process (RTP) step above 400° C. (e.g., about 450° C.) to form the metal-silicide material. Other low temperature process steps include deposition of an etch stop (Si3N4) layer and the deposition of a thick (e.g., 5000 Å) pre-metal dielectric (PMD) layer (typically SiO2) over the etch stop layer. The formation of the PMD layer can involve heating the wafer to 600° C. to 800° C. for minutes or hours.
The problems discussed above, including the dopant deactivation by subsequent low temperature processing steps, and variation in device characteristics by oxidation of the gate stack and adjacent silicon surfaces during the removal of the amorphous carbon optical absorber layer, are more critical in devices of smaller sizes (below 45 nm), and these problems must be solved in order enable fabrication of devices smaller than 45 nm.